Title: Layout Designer • Interpret schematics and floorplans to meet performance, area, and power targets. • At least 2 years of experience in FinFET nodes (7nm, 5nm, 3nm). • Solid understanding of physical verification (LVS/DRC/ERC), parasitic extraction, and reliability analysis. • Experience with RF, high-speed I/O, or power management layout is a plus.
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